NXP Semiconductors /MK66F18 /USBPHY /PLL_SIC_SET

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Interpret as PLL_SIC_SET

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)PLL_DIV_SEL 0 (PLL_EN_USB_CLKS)PLL_EN_USB_CLKS 0 (PLL_HOLD_RING_OFF)PLL_HOLD_RING_OFF 0 (PLL_POWER)PLL_POWER 0 (PLL_ENABLE)PLL_ENABLE 0 (PLL_BYPASS)PLL_BYPASS 0 (0)PLL_LOCK

PLL_DIV_SEL=00, PLL_LOCK=0

Description

USB PHY PLL Control/Status Register

Fields

PLL_DIV_SEL

This field controls the USB PLL feedback loop divider

0 (00): PLL reference frequency = 24MHz

1 (01): PLL reference frequency = 16MHz

PLL_EN_USB_CLKS

Enable the USB clock output from the USB PHY PLL.

PLL_HOLD_RING_OFF

Analog debug bit

PLL_POWER

Power up the USB PLL.

PLL_ENABLE

Enable the clock output from the USB PLL.

PLL_BYPASS

Bypass the USB PLL.

PLL_LOCK

USB PLL lock status indicator

0 (0): PLL is not currently locked

1 (1): PLL is currently locked

Links

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